1. Field Of the Invention
The present invention relates to high-density monolithic memories and, in particular, to the utilization of a hierarchical redundancy scheme to convert a partially functional memory chip into a fully functional chip thereby improving the overall yield of functional chips on a semiconductor wafer.
2. Discussion Of the Prior Art
As memory chip density increases, the defect density resulting from the integrated circuit fabrication process limits the functional yield. While an increasing amount of attention has been focused on controlling the fabrication process to limit defect density, as chip geometries shrink and chip size increases, it becomes increasingly difficult to control the process sufficiently to achieve a high natural functional yield.
A number of techniques, such as redundancy schemes, have been utilized to increase the functional yield of memory devices. A commonly used redundancy scheme provides spare rows and/or columns in the memory array that can be used to replace defective bits, rows or columns.
FIG. 1 shows a block diagram of a typical memory chip 10 with row and column redundancy. The memory array of chip 10 is subdivided into four quadrants Q0-Q3. "Quadrant" architecture is commonly used to enhance speed and to limit the power dissipation of memory chips. Memory cells within each quadrant are organized as n rows and m columns. A selected cell in the array is accessed by simultaneously applying a row address x.sub.n to the row decoders 12 and a column address y.sub.m to the column decoders 14 utilizing the address bus 15, thereby selecting a single row and a single column in the array. The intersection of the selected row and the selected column identifies the selected cell X.sub.n Y.sub.m. The data stored in that cell appears on the bit lines and is transferred to a sense amplifier (not shown) and then onto a data bus 16.
Writing to a selected memory cell is accomplished in a similar fashion, i.e., by first accessing the cell and then transferring the data to be written from the data bus 16 to the memory cell bit lines.
During the fabrication of a monolithic memory device, process defects can disable single or multiple cells, rows and/or columns in the array. As shown in FIG. 1, to overcome these defects, spare or redundant rows 18 and/or redundant columns 20 are provided. These spares can then be utilized to replace defective cells, rows and/or columns. If there is a defect in a given quadrant, causing a normal row 22 or a normal column 24 or a single bit to fail, then that particular row or column or bit is permanently disabled and is replaced by redundant row 18 or redundant column 20. The obvious limitation on the number of redundant rows and/or columns is the acceptable chip size and cost.
The redundancy scheme described above has several limitations. A redundant row can only replace a defective row or cells that are in the same row within the same quadrant. Similarly, a redundant column can only replace a defective column or cells that are in the same column, again within the same quadrant.